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Features
* PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors * A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge * Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS
* 5V/3.3V Regulator and Current Limitation Function * Reset Derived From 5V/3.3V Regulator Output Voltage * Sleep Mode With Supply Current of Typically < 45 A, Wake-up by Signal on Pins EN2 * * * * * *
or on LIN Interface A Programmable Window Watchdog Battery Overvoltage Protection and Battery Undervoltage Management Overtemperature Warning and Protection (Shutdown) LIN 2.0 Compliant 3.3V/5V Regulator with Trimmed Band Gap QFN32 Package
H-bridge Motor Driver ATA6823
1. Description
The ATA6823 is designed for several body and powertrain applications. The IC is used to drive a continuous current motor in a full H-bridge configuration. An external microcontroller controls the driving function of the IC by providing a PWM signal and a direction signal and allows the use of the IC in a motor-control application. The PWM control is performed by the low-side switch; the high-side switch is permanently on in the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for regulator and interface high level). The window watchdog has a programmable time, programmable by choosing a certain value of the external watchdog resistor RWD, internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.0 is integrated.
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Figure 1-1.
Block Diagram
M
CP VRES CPLO Charge Pump CPIH
RGATE H2
RGATE H1 S1 S2
RGATE L1
RGATE L2 PGND GND
HS Driver 2
HS Driver 1
LS Driver 1
LS Driver 2 VBAT OT UV DG3 DG2 DG1 CC CC timer
VG PBAT VBAT VINT
12V Regulator
Supervisor
OTP 12 bit
OV
Vint 5V Regulator Oscillator
Logic Control
WD timer EN2
CP
VBAT VBG VBATSW VCC 5V Regulator LIN Bandgap VCC WD EN1 VCC VMODE /RESET DIR PWM RX TX LIN
Battery
Microcontroller
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2. Pin Configuration
Figure 2-1. Pinning QFN32
EN2 VBATSW VBAT VCC PGND L1 L2 PBAT VMODE VINT RWD CC /RESET WD GND LIN 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 Atmel YWW 21 ATA6823 20 ZZZZZ-AL 19 18 17 9 10 11 12 13 14 15 16 TX DIR PWM EN1 RX DG3 DG2 DG1 VG CPLO CPHI VRES H2 S2 H1 S1
Note:
YWW ATA6823 ZZZZZ AL
Date code (Y = Year - above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Pin Description
Symbol VMODE VINT RWD CC /RESET WD GND LIN TX DIR PWM EN1 RX DG3 DG2 DG1 S1 H1 S2 H2 VRES I/O I I/O I I/O O I I I/O I I I I O O O O I/O O I/O O I/O Function Selector for VCC and interface logic voltage level Blocking capacitor 220 nF/10V/X7R Resistor defining the watchdog interval RC combination to adjust cross conduction time Reset signal for microcontroller Watchdog trigger signal Ground for chip core LIN-bus terminal Transmit signal to LIN bus from microcontroller Defines the rotation direction for the motor PWM input controls motor speed Microcontroller output to keep the chip in Active mode Receive signal from LIN bus for microcontroller Diagnostic output 3 Diagnostic output 2 Diagnostic output 1 Source voltage H-bridge, high-side 1 Gate voltage H-bridge, high-side 1 Source voltage H-bridge, high-side 2 Gate voltage H-bridge, high-side 2 Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R
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Table 2-1.
Pin 22 23 24 25 26 27 28 29 30 31 32
Pin Description (Continued)
Symbol CPHI CPLO VG PBAT L2 L1 PGND VCC VBAT VBATSW EN2 I/O I O I/O I O O I O I O I Function Charge pump capacitor 220 nF/25V/X7R Blocking capacitor 470 nF/25V/X7R Power supply (after reverse protection) for charge pump and H-bridge Gate voltage H-bridge, low-side 2 Gate voltage H-bridge, low-side 1 Power ground for H-bridge and charge pump 5V/100 mA supply for microcontroller, blocking capacitor 2.2 F/10V/X7R Supply voltage for IC core (after reverse protection) 100 PMOS switch from VBAT Enable input
3. General Statement and Conventions
* Parameter values given without tolerances are indicative only and not to be tested in production * Parameters given with tolerances but without a parameter number in the first column of parameter table are "guaranteed by design" (mainly covered by measurement of other specified parameters). These parameters are not to be tested in production. The tolerances are given if the knowledge of the parameter tolerances is important for the application * The lowest power supply voltage is named GND * All voltage specifications are referred to GND if not otherwise stated * Sinking current means that the current is flowing into the pin (value is positive) * Sourcing current means that the current is flowing out of the pin (value is negative)
3.1
Related Documents
* Qualification of integrated circuits according to Atmel(R) HNO procedure based on AEC-Q100 * AEC-Q100-004 and JESD78 (Latch-up) * ESD STM 5.1-1998 * CEI 801-2 (only for information regarding ESD requirements of the PCB)
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4. Application
4.1 General Remark
This chapter describes the principal application for which the ATA6823 was designed. Because Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given.
Table 4-1.
Component CVINT CVCC CCC RCC CVG CCP CVRES RRWD CLIN
Typical External Components
Function Blocking capacitor at VINT Blocking capacitor at VCC Cross conduction time definition capacitor Cross conduction time definition resistor Blocking capacitor at VG Charge pump capacitor Reservoir capacitor Watchdog time definition resistor Filter capacitor for LIN bus Value 220 nF, 10V, X7R 2.2 F, 10V, X7R Typical 330 pF, 100V, COG Typical 10 k 470 nF, 25V, X7R 220 nF, 25V, X7R 470 nF, 25V, X7R Typical 51 k Typical 220 pF, 100V 10% 10% 10% 1% 10% Tolerance 10% 10%
5. Functional Description
5.1
5.1.1
Power Supply Unit with Supervisor Functions
Power Supply The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT pin of the IC (see Figure 1-1 on page 2). A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor provides the necessary low-voltage supply needed for the wake-up process. The low-power band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks are supplied by the internal regulator.
Note: The internal supply voltage VINT must not be used for any other supply purpose!
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator. A power-good comparator checks the output voltage of the VINT regulator and keeps the whole chip in reset as long as the voltage is too low. There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset going to sleep mode, VBATSW turns OFF. The signal can be used to switch on external voltage regulators, etc.
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5.1.2
Voltage Supervisor This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it. Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz.
5.1.3
Temperature Supervisor There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry and to protect the external NMOSFET transistors. In case of detected overtemperature (150C), the diagnostic pin DG3 will be switched to "H" to signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (165C), the VCC regulator and all drivers including the LIN transceiver will be switched OFF immediately and /RESET will go LOW. Both temperature thresholds are correlated. The absolute tolerance is 10C and there is a built-in hysteresis of about 10C to avoid fast oscillations. After cooling down below the 155C threshold; the IC will go into Active mode. The LIN interface has a separate thermal shutdown with disabled the low-side driver at typically 165C.
5.2
Sleep Mode
To be able to guarantee the low quiescent current of the inactive IC, a Sleep mode is established. In Sleep mode it is possible to wake-up the IC by using the pins EN2 or LIN. In Sleep mode, the following blocks are active: * Band gap * Internal 5V regulator (VINT) with external blocking capacitor of 220 nF * Input structure for detecting the EN2 pins threshold * Wake-up block of the LIN receive part
5.3
Wake-up and Sleep Mode Strategy
The IC has two modes: Sleep and Active. The change between the modes is described below. The default state after power-on is Active mode. The wake-up procedure brings the IC from a standby mode (Sleep) to an active mode (Active). The internal 5V supply VINT, the EN2 pin input structure and a certain part of the LIN receiver are permanently active to ensure a proper startup of the system. The Go to Active and Go to Sleep procedures are implemented as follows: * Go to Active by activating pin EN2 The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists of a comparator with built-in hysteresis. It is ESD-protected by diodes against GND and VBAT; for this reason the input voltage level must be positive and not higher than VBAT.
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Pulling the EN2 pin up to the VBAT level will drive the IC into Active mode. EN2 is debounced with a time constant of 20 s, based on a 100 kHz clock. * Go to Active using the LIN interface The second possibility for wake-up can be performed using the LIN transceiver. In Sleep mode, the LIN receiver is partially active. The wake-up by LIN requires 2 steps: 1. If the voltage on pin LIN is below a value of V/DATwake (about VVBAT - 2V) the receive part of the LIN interface is active (not to be confused with Active mode of the whole IC). The active receive part is able to detect a valid LOW on the LIN pin. 2. If LIN = LOW during a filter time twakeLIN (typically 70 s) the IC will change to Active mode. A short change back to HIGH during the filter time will reset the filter. This information is stored in a latch after entering Active mode If the change to Active mode was caused by LIN, the EN1 or EN2 pins may remain LOW without disturbing the Active mode. * Stay in Active via EN1 The input EN1 is intended to keep the IC in Active Mode via a signal from the microcontroller. The input is ESD-protected by diodes against GND and VCC. Therefore, the input voltage must be positive and not higher than VCC. EN1 cannot be used to switch from Sleep to Active because the VCC regulator is off in the Sleep mode and VCC will be zero. * Go to Sleep A HIGH to LOW transition at pin EN1 and a following permanent LOW for the time t gotosleep (typically 20 s) switches the IC to Sleep mode. Figure 5-1 illustrates the wake-up by LIN. The status PREWAKE is characterized by the activated receive block of the LIN interface. After going to Active mode, the VCC regulator starts working. Go to Sleep is possible with a valid HIGH to LOW transition at pin EN1 (permanent LOW for longer than tdb) if EN1 was in a valid HIGH state (HIGH for longer than tdb) before.
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Figure 5-1.
LIN VBAT
Wake-up by pin LIN
55% VBAT 45% VBAT
VBAT - 1.5V activating "PREWAKE"
t
EN1 tdb
t
RX t < twake LIN twake LIN
t
STATUS ACTIVE tdb
SLEEP
t
5.4
5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 F ceramic capacitor for stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage. The output voltage accuracy is in general < 3%; in the 5V mode with VVBAT < 8V it is limited to < 5%. To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 160 mA to 320 mA. The delivered voltage will break down and a reset may occur. Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink.
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A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low. Figure 5-2. Correlation between VCC Output Voltage and Reset Threshold
5.15V 4.9V VCC1 4.85V VtHRESH 4.1V
VCC1-VtHRESH = VCC1 - VtHRESH
The voltage difference between the regulated output voltage and the upper reset threshold voltage is higher than 100 mV.
5.5
Reset and Watchdog Management
The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is adjustable via the external resistor RWD. The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time window of TWD. In order to save current consumption, the watchdog is switched off during Sleep mode.
Figure 5-3.
Timing Diagram of the Watchdog Function
tres tresshort
/RESET td t1 t2 t1 t2 td
WD
5.5.1
Timing Sequence For example, with an external resistor RWD = 33 k 1% we get the following typical parameters of the watchdog. TOSC = 12.32 s, t1 = 12.1 ms, t2 = 9.61 ms, TWD = 16.88 ms 10% The times tres = 68 ms and td = 68 ms are fixed values with a tolerance of 10%.
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After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low for the time tres (typically 68 ms), then switches to high. For an initial lead time td (typically 68 ms for setups in the controller) the watchdog waits for a rising edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the watchdog will reset the microcontroller for tres and wait td for the rising edge on WD. Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the timeframe of t2 = 9.61 ms. The trigger event will restart the watchdog sequence. Figure 5-4. TWD versus RWD
60
50 max
typ
TWD (ms)
40
30 min 20
10
0 10 20 30 40 50 60 70 80 90 100
RWD (k)
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms. The watchdog start sequence is similar to the power-on reset. The internal oscillator is trimmed to a tolerance of < 10%. This means that t1 and t2 can also vary by 10%. The following calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide. t1min = 0.90 x t1 = 10.87 ms, t1max = 1.10 x t1 = 13.28 ms t2min = 0.90 x t2 = 8.65ms, t2max = 1.10 x t2 = 10.57 ms Twdmax = t1min + t2min = 10.87 ms + 8.65 ms = 19.52 ms Twdmin = t1max = 13.28 ms Twd = 16.42 ms 3.15 ms (19.1%) Figure 5-4 above shows the typical watchdog period TWD depending on the value of the external resistor ROSC. A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth).
5.6
LIN Transceiver
A bi-directional bus interface is implemented for data transfer between the LIN bus and the local LIN protocol controller. The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shaping, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver.
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5.6.1 Transmit Mode During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin LIN. To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave-shaping unit. Transmission will be interrupted in the following cases: * Thermal shutdown active or overtemperature LIN active * Sleep mode Figure 5-5. Definition of Bus Timing Parameters
tBit TXD
(input to transmitting Node)
tBit
tBit
tBus_dom(max)
tBus_rec(min)
THRec(max) VS
(Transceiver supply of transmitting node)
Thresholds of receiving node 1 LIN Bus Signal
THDom(max) Thresholds of receiving node 2
THRec(min) THDom(min)
tBus_dom(min) RXD
(output of receiving Node 1)
tBus_rec(max)
trx_pdf(1) RXD
(output of receiving Node 2)
trx_pdr(1)
trx_pdr(2)
trx_pdf(2)
The recessive BUS level is generated from the integrated 30 k pull-up resistor in series with an active diode. This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS > VSUP). No additional termination resistor is necessary to use the ATA6823 in LIN slave nodes. If this IC is used for LIN master nodes, it is necessary that the BUS pin be terminated via an external 1 k resistor in series with a diode to VBAT. 5.6.2 TXD Dominant Time-out Function The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced low longer than tdom > 18.4 ms, the pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (> 10 s) before switching LIN to dominant again.
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5.7
5.7.1
Control Inputs EN1, EN2, DIR, PWM
Pins EN1, EN2 Any of the enable pins may be used to activate the IC with a HIGH. EN1 is a low level input, EN2 has to withstand a voltage up to 40V. Internal pull-down resistors are included.
5.7.2
Pin DIR Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is included.
5.7.3
Pin PWM Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included.
Table 5-1.
ON 0 1 1 DIR X 0 1
Status of the IC Depending on Control Inputs and Detected Failures
Driver Stage for External Power MOS H1 OFF ON /PWM L1 OFF OFF PWM H2 OFF /PWM ON L2 OFF PWM OFF Standby mode Motor PWM forward Motor PWM reverse X PWM PWM Comments PWM
Control Inputs
The internal signal ON is high when * At least one valid trigger has been accepted (SYNC = 1) * VBAT is inside the specified range (UV = 0 and nOV = 1) * The charge pump has reached its minimum voltage (CPOK = 1) and * The device is not overheated (OT2 = 0) In case of a short circuit, the appropriate transistor is switched off after a debounce time of about 10 s. In order to avoid cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC combination.
Table 5-2.
CPOK 0 X X X X Note:
Status of the Diagnostic Outputs
Device Status OT1 X 1 X X OV X X 1 X UV X X X 1 SC X X X X Diagnostic Outputs DG1 - - - - DG2 1 - 1 1 - DG3 - 1 - - - Charge pump failure Overtemperature warning Overvoltage Undervoltage Short circuit Comments
X X X 1 1 X represents: don't care - no effect) OT1: Overtemperature warning OV: Overvoltage of VBAT UV: Undervoltage of VBAT SC: Short circuit CPOK: Charge pump OK
In order to be able to distinguish between a wake-up from LIN or from EN2, the source of wake-up is flagged in DG1 until the first valid trigger (LIN = 0, EN2 = 1). 12
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5.8 VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage is reduced if the supply voltage at VBAT falls below 12V.
5.9
Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the output voltage on the reservoir capacitor is VBAT plus VG. The charge pump is clocked with a dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC level.
5.10
Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning level will be reached at 150C. At this point the IC stays fully functional and a warning will be sent to the microcontroller. At junction temperature 165C the VCC regulator will be switched off and a reset occurs.
5.11
H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side drivers and two push-pull drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and logic-level power NMOS. The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is possible to control the external load (motor) in the forward and reverse direction (see Table 5-1 on page 12). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in both directions.
5.11.1
Cross Conduction Time To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in the following way: tCC (s) = 0.41 x RCC (k) x CCC (nF) (tolerance: 5% 0.15 s) The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level. The resistor RCC must be greater than 5 k and should be as close as possible to 10 k, the CCC value has to be 5 nF. Use of COG capacitor material is recommended. The time measurement is triggered by the PWM or DIR signal crossing the 50% level.
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Figure 5-6.
Timing of the Drivers
PWM or DIR
50%
t
tLxHL tLxf tLxLH tLxr
80%
Lx
20%
tCC
t
tHxLH tHxr tHxHL tHxf
tCC
80%
Hx
20%
t
The delays tHxLH and tLxLH include the cross conduction time tCC.
5.12
Short Circuit Detection
To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS. If the transistors are switched ON and the source-drain voltage difference is higher than the value VSC (4V with tolerances) for a time > tSC (typically 10 s) the signal SC (short circuit) will be set and the drivers will be switched off immediately. The diagnostic pin DG1 will be set to "H". With the next transition on pin PWM, the bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on again. There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time > tSC the drivers will be switched off immediately and DG1 will be set to "H". It will be cleared as above.
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6. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description Ground Power ground Reverse protected battery voltage Reverse protected battery voltage Digital output Digital output 4.9V output, external blocking capacitor Cross conduction time capacitor/resistor combination Digital input coming from microcontroller Watchdog timing resistor Digital input direction control Digital input PWM control + Test mode Digital input for enable control Digital input for enable control 5V regulator output Digital input 12V output, external blocking capacitor Digital output Digital input LIN data pin Source external high-side NMOS Gates external low-side NMOS Gates of external high-side NMOS Charge pump Charge pump Charge pump output Switched VBAT Power dissipation Storage temperature Soldering temperature (10s) Notes: 1. For VVBAT 13.5V 2. May be additionally limited by external thermal resistance Pin Name GND PGND VBAT PBAT /RESET DG1, DG2, DG3 VINT CC WD RWD DIR PWM EN1 EN2 VCC VMODE VG RX TX LIN S1, S2 L1, L2 H1, H2 CPLO CPHI VRES VBATSW Ptot STORE SOLDERING -40 Min 0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -27
(1)
Max 0 +0.3 +40 +40 VVCC + 0.3 VVCC + 0.3 +5.5 VVINT + 0.3 VVINT + 0.3 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 VVBAT + 0.3 +5.5 VVINT + 0.3 +16 VVCC + 0.3 VVCC + 0.3 VVBAT + 2 +30 VVG + 0.3 VS + 16 VPBAT + 0.3 VVRES + 0.3 +30 VVBAT + 0.3 1.4
(2)
Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V W C C
-2 VPGND - 0.3 VS - 1 -0.3 -0.3 -0.3 -0.3
+150 240
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7. Thermal Resistance
Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient when heat slug is soldered to PCB Symbol Rthjc Rthja Value <5 25 Unit K/W K/W
8. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly. Parameters Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Normal functionality Normal functionality, overtemperature warning Drivers for H1, H2, L1, L2, and LIN are switched OFF, VCC regulator is OFF Note: 1. Full functionality 2. H-bridge drivers may be switched off (undervoltage detection) 3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly 4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct 5. H-bridge drivers are switched off
(1)
Symbol VVBAT1 VVBAT2 VVBAT3 VVBAT4 VVBAT5 Ta Ta Ta Ta
Min 7 6 3 0 > 20 -40 -40 150 165
Max 18 <7 <6 <3 40 +125 +125 165 180
Unit V V V V V C C C C
Operating supply voltage(2)
(3) (4) (5)
Ambient temperature range under bias
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9. Electrical Characteristics
All parameters given are valid for 7V VBAT 18V and for -40C ambient 125C unless stated otherwise. No. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Parameters Test Conditions Pin 25, 30 25, 30 2 Symbol IVBAT1 IVBAT2 VINT VBG 30 Measured during qualification only 30 30 Measured during qualification only VVBAT = 13.5V 30 31 VTHOV VTOVhys VTHUV VTUVhys RON_VBATSW 4.8 1.225 19.8 1 6.5 0.2 4.94 1.235 Min Typ Max 7 50 5.1 1.245 22.3 1.5 7 0.4 100 Unit mA A V V V V V V Type* A A A A A A A A A Power Supply and Supervisor Functions Current consumption VBAT VVBAT = 13.5V(1) Current consumption VBAT VVBAT =13.5V in Standby mode Internal power supply Band gap voltage Overvoltage threshold VBAT Overvoltage threshold hysteresis VBAT Undervoltage threshold VBAT Undervoltage threshold hysteresis VBAT On resistance of VBAT switch 5V/3.3V Regulator Regulated output voltage Regulated output voltage Line regulation Load regulation Output current limitation Serial inductance to CVCC including PCB Serial resistance to CVCC including PCB Blocking cap at VCC
(2), (3)
9V < VVBAT < 40V Iload = 0 mA to 100 mA 6V < VVBAT 9V Iload = 0 mA to 100 mA Iload = 0 mA to 100 mA Iload = 0 mA to 100 mA VVBAT > 6V
29 29 29 29 29 29 29 29
VCC1 VCC2 DC line regulation DC load regulation IOS1 ESL ESR CVCC
4.85 (3.2) 4.75 (3.2) <1 <10 100 1 0 1.5
5.15 (3.4) 5.25 (3.4) 50 50 300 20 0.5 3.0
V V mV mV mA nH F
A A A A C D D D
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
17
4856F-AUTO-01/08
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 125C unless stated otherwise. No. 2.9 2.10 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Parameters HIGH threshold VMODE LOW threshold VMODE Reset and Watchdog VCC threshold voltage level for /RESET VCC threshold voltage level for /RESET Hysteresis of /RESET level Length of pulse at /RESET pin Length of short pulse at /RESET pin Wait for the first WD trigger Time for VCC < VtHRESL before activating /RESET Resistor defining internal bias currents for watchdog oscillator Watchdog oscillator period Watchdog oscillator period with internal resistor Watchdog input low-voltage threshold Watchdog input high-voltage threshold Hysteresis of watchdog input voltage threshold Close window
(5)
Test Conditions
Pin 1 1
Symbol VMODE H VMODE L
Min 0.7
Typ
Max 4.0
Unit V V
Type* A A
VMODE = "H" (VMODE = "L") VMODE = "H" (VMODE = "L") VMODE = "H" (VMODE = "L")(4)
(5)
29 29 29 5 5 5 29
VtHRESH VtHRESL HYSRESth tres tresshort td tdelayRESL RRWD TOSC TOSC_start 0.5 4.1 (2.7) 70 0.2 6800 200 6800
4.6 (3.05)
V V
A A A A A A C
350 (220)
V T100 T100 T100
(5)
(5)
(4)
2
s
3.8
3
10
91
k
D
3.9
RRWD = 33 k
3
11.09
13.55
s
A
3.10
16
24 0.3 x VVCC
s
A
3.11 3.12 3.13 3.14
6 6 6
VILWD VIHWD VhysWD t1 0.7 x VVCC 1 980 x TOSC
V V V
A A A A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
18
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9. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 125C unless stated otherwise. No. 3.15 3.16 3.17 4 4.1 Parameters Open window Output low-voltage of /RESET Internal pull-up resistor at pin /RESET Lin Transceiver Low-level output current Normal mode; VLIN = 0V, VRX = 0.4V Normal mode; VLIN = VBAT VRX = VCC - 0.4V VTXD = 0V; ILIN = 0 mA VVAT = 7.3V Rload = 500 VVAT = 18V Rload = 500 VVAT = 7.3V Rload = 1000 VVAT = 18V Rload = 1000 The serial diode is mandatory VBUS = VBAT_max Input leakage current driver off VBUS = 0V VBAT = 12V Driver off 8V < VBAT < 18V 8V < VBUS < 18V VBUS VBAT 13 ILRX IHRX VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN IBUS_LIM IBUS_PAS_dom 0.6 0.8 20 50 30 60 200 4 mA D Test Conditions
(5)
Pin
Symbol t2
Min
Typ 780 x TOSC
Max
Unit
Type* A
At IOLRES = 1 mA
5 5
VOLRES RPURES 5 10
0.4 15
V k
A D
4.2
High-level output current Driver recessive output voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Pull up resistor to VS Current limitation Input leakage current at the receiver including pull-up resistor as specified Leakage current LIN recessive
13
4 0.9 x VBAT 1.2 2
mA
D
4.3 4.4 4.5 4.6 4.7 4.8 4.9
8 8 8 8 8 8 8
V V V V V k mA D
4.10
8
-1
mA
4.11
8
IBUS_PAS_rec
20
A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
19
4856F-AUTO-01/08
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 125C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type* Leakage current at ground loss Control unit disconnected GNDDevice = VS from ground VBAT =12V Loss of local ground must 0V < VBUS < 18V not affect communication in the residual network Node has to sustain the current that can flow VBAT disconnected under this condition. Bus VSUP_Device = GND must remain operational 0V < VBUS < 18V under this condition Center of receiver threshold Receiver dominant state Receiver recessive state Dominant time for wake-up via LIN-bus Input low-voltage threshold Input high-voltage threshold Hysteresis Pull-down resistor Pull-up resistor Rise/fall time Debounce time EN1 Charge Pump Charge pump voltage Charge pump voltage Load = 0A Load = 3 mA, CCP = 100 nF 21 21 VCP VCP VVBAT + VVG - 1 VVBAT + VVG V V A A
(6) (6)
4.12
8
IBUS_NO_gnd
-1
1
mA
4.13
8
IBUS
100
A
4.14 4.15 4.16 4.17 4.18 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6 6.1 6.2
VBUS_CNT = (Vth_dom + Vth_rec)/2 VEN = 5V VEN = 5V
8 8 8 8 8
VBUS_CNT VBUSdom VBUSrec VBUShys TBUS
0.475 VS
0.5 VS
0.525 VS 0.4 VS
V V V V s D
0.6 VS 0.1 VS 30 90 0.175 VS 150
Receiver input hysteresis VHYS = Vth_rec - Vth_dom VLIN = 0V
Control Inputs EN1, DIR, PWM, WD, TX VIL VIH HYS RPD RPU trf tdb 2 x T100 25 25 0.7 x VVCC 0.7 50 50 100 100 100 3 x T100 k k ns s 0.3 x VVCC V V A A A D D D D
EN1, DIR, PWN, WD TX
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
20
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ATA6823
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 125C unless stated otherwise. No. 6.3 6.4 6.5 7 7.1 7.2 7.3 Parameters Period charge pump oscillator CP load current in VG without CP load CP load current in VG with CP load H-bridge Driver Low-side driver HIGH output voltage ON-resistance of sink stage of pins L1, L2 ON-resistance of source stage of pins L1, L2 Output peak current at pins L1, L2, switched to LOW Output peak current at pins L1, L2, switched to HIGH Pull-down resistance at pins L1, L2 ON-resistance of sink stage of pins H1, H2 ON-resistance of source stage of pins H1, H2 VSx = 0 VSx = VVBAT VLx = 3V VLxH RDSON_LxL, x = 1, 2 RDSON_LxH, x = 1, 2 ILxL, x = 1, 2 ILxH, x = 1, 2 RPDLx x = 1, 2 RDSON_HxL, x = 1, 2 RDSON_HxH, x = 1, 2 IHxL, x = 1, 2 IHxH, x = 1, 2 VHxL, x = 1, 2 100 30 100 VVG 20 20 V mA D A A Load = 0A Load = 3 mA, CCP = 100 nF Test Conditions Pin Symbol T100 IVGCPz IVGCP Min 9 Typ Max 11 100 3.3 Unit s A mA Type* A D A
7.4
D
7.5
VLx = 3V
-100
mA
D
7.6 7.7 7.8
100 20 20
k mA
A A A
7.9
VVBAT = 13.5V Output peak current at V = VVBAT pins Hx, switched to LOW Sx VHx = VVBAT + 3V Output peak current at pins Hx, switched to HIGH Static high-side switch output low-voltage pins Hx VVBAT = 13.5V VSx = VVBAT VHx = VVBAT + 3V VSx = 0V IHx = 1 mA
D
7.10
-100
mA
D
7.11
0.3
V
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
21
4856F-AUTO-01/08
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 125C unless stated otherwise. No. 7.12 Parameters Static high-side switch output high-voltage pins H1, H2 Sink resistance between Hx and ground in Sleep mode Dynamic Parameters 7.14 Dynamic high-side switch CHx = 5 nF output high-voltage pins CCB = 100 nF fPWM = 20 kHz H1, H2 Propagation delay time, low-side driver from high to low Propagation delay time, low-side driver from low to high Fall time low-side driver Rise time low-side driver Propagation delay time, Figure 5-6 on page 14 high-side driver from high VVBAT = 13.5V to low Propagation delay time, high-side driver from low to high Fall time high-side driver Rise time high-side driver Cross conduction time External resistor External capacitor RON of tCC switching transistor
(8)
Test Conditions ILx = -10 A (PWM = static)
Pin
Symbol VHxHstat1(7)
Min VVBAT + VVG - 1 3
Typ
Max VVBAT + VVG 10
Unit V
Type*
7.13
RHxsleep
k
VHxHdyn1
VVBAT + VVG - 1
VVBAT + VVG 0.5
V
7.15
Figure 5-6 on page 14 VVBAT = 13.5V
tLxHL
s
7.16
tLxLH VVBAT = 13.5V CGx=5 nF tLxf tLxr tHxHL
0.5 + tCC 0.5 0.5 0.5
s
7.17 7.18 7.19
s s s
7.20
tHxLH VVBAT = 13.5V, CGx = 5 nF tHxf tHxr tCC RCC CCC RONCC 5
0.5 + tCC 0.5 0.5 10 5 100
s
7.21 7.22 7.23 7.24 7.25 7.26
s s s k nF
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
22
ATA6823
4856F-AUTO-01/08
ATA6823
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 125C unless stated otherwise. No. 7.27 7.28 7.29 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 Parameters Switching level of tCC comparator Short circuit detection voltage Short circuit detection time Input EN2 Input low-voltage threshold Input high-voltage threshold Hysteresis Pull-down resistor Rise/fall time Debounce time Low level output current High level output current
(6) (6) (9)
Test Conditions
Pin
Symbol Vswtcc VSC tSC
Min 0.653 x VVCC 3.5 5
Typ 0.667 x VVCC 4 10
Max 0.68 x VVCC 4.5 15
Unit V V ms
Type*
(10)
VIL VIH HYS RPD trf tdb IL IH
2.3 2.8 0.47 50 2 x T100 4 4 100
3.6 4.0
V V V
200 100 3 x T100
k ns s mA mA
Diagnostic Outputs DG1, DG2, DG3 VDG = 0.4V(6) VDG = VCC - 0.4V(6)
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
23
4856F-AUTO-01/08
10. Schaffner and Electromagnetic Compatibility
10.1 Transients on Power-supply Rail (Battery)
The application (including IC and external protection circuitry, see Figure 1-1 on page 2) has to withstand the test pulses in Table 10-1.
Table 10-1.
Test Pulse No. 1 2 3a 3b 4 5
Test Pulses
Test Level -100V 150V -200V 200V 4V/5.5V 40V Duration or Number of Pulses 10 min 10 min 10 min 10 min 15 ms/2s 5 pulses, 1 minute recurrence period Specs Ri = 10 Ri = 10 Ri = 50 Ri = 50 Ri = 0.01 Ri = 0.5, td = 400 ms, tr = 5 ms Acceptance level A A A A A B
Figure 10-1. Pulse 1 (Ri = 10)
V 200 ms < 100 s 12V 10%
t
90% -100V 1 s 1 ms 5s
Figure 10-2. Pulse 2 (Ri = 10)
200 ms V 150V 90% 50 s 2 s
10% 12V 50 s
t
24
ATA6823
4856F-AUTO-01/08
ATA6823
Figure 10-3. Pulse 3a (Ri = 50)
100 ns V 12V 10 ms 90 ms 5 ns
t
10%
90% -200V 100 s
Figure 10-4. Pulse 3b (Ri = 50)
V 200V 90% 100 s
10% 12V 10 ms 90 ms
t
5 ns 100 ns
Figure 10-5. Pulse 4 (Ri = 0.01)
12V
5.5V
4.0V
0V < 5 ms 15 ms 50 ms 2000 ms 100 ms
t
25
4856F-AUTO-01/08
10.2
Transients on Pin LIN
Transients to these pins are coupled capacitively to the IC and are valid for the application with external circuitry concerning figure 6. Values: Pulse 3a, Pulse 3b (see Figure 10-3 and Figure 10-4 on page 25) coupled via 1 nF to LIN, Ri = 50 Acceptance level A
10.3
Conducted Emissions, Radiated Emissions and Susceptibility
The application using the IC described in this specification has to fulfill the demands of the following specifications: * GM GMW3100 (2001-08) * TL82166 (1998-02) * TL82366 (2002-03) * TL965 (1999-10) It is the responsibility of both the deliverer and the user of the described IC to meet the mentioned specifications.
11. ESD and Latch-up Requirements
The device withstands pulses when tested according to ESD STM 5.1-1998: * Constant voltage 2 kV * R = 1.5 k * C = 100 pF 1 pulse per polarity and per pin 3 samples, 0 failures Electrical post stress testing at room temperature Static latch-up tested according to AEC-Q100-004 and JESD78. * 3 to 6 samples, 0 failures * Electrical post stress testing at room temperature In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when not able to drive the specified current.
26
ATA6823
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12. Ordering Information
Extended Type Number ATA6823-PHQW Package QFN32 Remarks Pb-free
13. Package Information
Package: QFN 32 - 7 x 7 Exposed pad 4.7 x 4.7 Dimensions in mm Not indicated tolerances 0.05 0.90.1 0.05-0.05 32 1 24 25 32 1
technical drawings according to DIN specifications +0
7 4.7
8 0.3 0.6
17 16 0.65 nom. 4.55 9
8
Drawing-No.: 6.543-5097.01-4 Issue: 1; 24.02.03
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4856F-AUTO-01/08 4856E-AUTO-07/07 History * Section 5.4 "5V/3.3V VCC Regulator" on pages 8 to 9 changed * Section 10 "Electrical Characteristics" number 3.3 on page 18 changed * Section 12 "Ordering Information" on page 27 changed * Put datasheet in a new template
27
4856F-AUTO-01/08
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4856F-AUTO-01/08

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